Field of the Invention
The present patent application relates to a method for etching a layer in a trench and to methods for fabricating a trench capacitor. The trench capacitor is particularly suitable for a memory cell of a semiconductor memory.
Semiconductor memories, such as for example DRAMs (dynamic random access memories) comprise a cell array and driving peripherals. The cell array contains a multiplicity of individual memory cells.
The cell array of a DRAM chip includes a matrix of memory cells which are arranged in the form of rows and columns and are driven by word lines and bit lines. The reading of data from the memory cells or the writing of data to the memory cells is effected by the activation of suitable word lines and bit lines.
A memory cell of a DRAM usually includes a transistor which is connected to a capacitor. The transistor comprises two doping regions which are separated from one another by a channel, which is controlled by a gate. One doping region is referred to as a drain region, and the other doping region is referred to as a source region. One of the diffusion regions is connected to a bit line, the other diffusion region is connected to a capacitor and the gate is connected to a word line. When a memory cell is accessed, the transistor is made conductive by application of suitable voltages to the gate, and the capacitor is connected to the bit line via the transistor.
The on-going miniaturization of memory components has led to a continuous increase in the integration density. The result of the continuous increase in the integration density is that the surface area available for each memory cell is becoming ever smaller. This means that the select transistor and the storage capacitor of a memory cell are subject to a constant reduction in their geometric dimensions.
The on-going efforts to reduce the size of the memory devices promotes the designing of DRAMs with a high density and smaller feature size in order to achieve a smaller memory-cell area. Smaller components, such as for example capacitors, are used to fabricate memory cells which require a small surface area. However, the use of small capacitors results in a lower storage capacitance in the individual capacitor, which in turn may have an adverse effect on the functionality and usability of the memory device.
By way of example, read amplifiers require a sufficient signal level to reliably read the information item which is stored in the memory cells. The ratio of the storage capacitance to the bit line capacitance is crucial in the determination of the signal level. If the storage capacitance is too low, this ratio may be too low to generate a sufficient signal to drive the read amplifier. Also, a lower storage capacitance requires a higher refresh frequency.
By way of example, HSG (hemispherical silicon grains) are known to increase the storage capacitance. An etching mask is usually required in order to structure these grains and in general terms to structure a material with the aid of a dry-etching process, this mask ensuring that the material below the etching mask is locally retained while the material in the areas which are not protected by the etching mask is removed. The removal of nanocrystallites, such as for example HSG (hemispherical silicon grains), from the upper region of a trench capacitor of a DRAM represents a special case in connection with this general problem. The HSG is usually removed from the region of the insulation collar, in order, for example, to avoid a short circuit between the buried outer capacitor electrode and the inner capacitor electrode.
For this purpose, by way of example, photoresist or polycrystalline silicon could be introduced into the lower region of the trench, in order to protect the trench sidewall and the HSG already present thereon. Therefore, the HSG can be removed from the upper region of the trench. However, a drawback in this case is that a considerable process outlay is required, for example the introduction and patterning of the protective layer and the subsequent removal of the protective layer from the lower region of the trench.
Commonly assigned German patent DE 199 47 053 C1 describes a trench capacitor for use in a memory cell of a DRAM, and a corresponding fabrication method. The trench capacitor has a trench that is directed from the surface of the semiconductor substrate into the interior of the substrate and has an upper section, defined by a collar oxide, and a lower section, directed toward the interior of the substrate. A dielectric layer is deposited on the trench sidewalls of the lower section and on the collar oxide of the upper section. The dielectric layer may consist of tungsten oxide. According to one embodiment, a barrier layer may be laid beneath the dielectric layer in the upper and lower sections of the trench. The barrier layer may consist of tungsten nitride.